The present invention relates to DC-DC converters, and more particularly to a DC-DC converter for low-voltage high-current applications.
FIG. 1 shows a known DC-DC converter which is described in Japanese Patent 62-032702. The primary circuit of the known converter includes a full-bridge switching circuit formed by a first series circuit of transistors Q1 and Q2 and a second series circuit of transistors Q3 and Q4 connected in parallel between a positive input terminal 1 and a negative input terminal 2 across which a noise-suppressing capacitor C1 is coupled. The primary winding 10 of a step-down transformer T1 and an anti-biasing capacitor CT are connected in series across a junction between transistors Q3, Q4 and a junction between transistors Q1, Q2. The transformer has two secondary windings 11, 12. The dotted terminal (or instantaneously positive terminal) of winding 11 is coupled through a diode D1 to one end of a smoothing inductor L1, the undotted (instantaneously negative) terminal of the winding being coupled through a diode D2 to inductor L1. These diodes form a halfwave rectifier. Whereas, for winding 12, the undotted terminal is coupled through a diode D3 to one end of a smoothing inductor L2, the dotted terminal being coupled through a diode D4 to inductor L2. The other ends of inductors L1 and L2 are connected together to a positive output terminal 3 and the undotted terminal of winding 11 and the dotted terminal of winding 12 are connected together to a negative output terminal 4. A smoothing capacitor C0 is connected across output terminals 3 and 4. The bases of transistors Q1.about.Q4 are coupled to a variable duration pulse generator 13 to which the DC output voltage is applied to control the duration of the turn-on pulses.
Transistors Q1 and Q4 are turned on simultaneously in response to gate-on pulses from pulse generator 13 and then transistors Q2 and Q3 are turned on so that voltage pulses of opposite polarities are successively generated in the primary winding of transformer T1, and voltage pulses of equal magnitude but opposite polarities are induced respectively in the secondary windings 11 and 12. Diodes D1 and D3 are alternately turned on, charging capacitor C0. Diodes D2 and D4 are turned on successively in response to the turn-off of diodes D1 and D3, respectively, to cause energies stored in inductors L1 and L2 to be discharged into capacitor C0 to develop a DC voltage across terminals 3 and 4.
However, the turn-on time of transistors Q1, Q4 may differ from the turn-on time of transistors Q2, Q3 and the core of transformer T1 is magnetically biased in one direction. A DC voltage corresponding to the timing difference develops in the primary winding 10. Capacitor CT provides a feedback circuit for supplying the DC voltage to transistors Q1, Q2 to reduce the effect of the magnetic bias of the transformer core.
Because of the use of two secondary windings, the prior art DC-DC converter is too bulky for applications where large output currents are required. In addition, when all transistors are in an OFF state, diodes D2 and D4 are in a conducting state and two low-impedance loops are formed, one comprising the secondary winding 11 and diodes D1, D2, and the other comprising the secondary winding 12 and diodes D3, D4. It is found that a difference in impedance between these low-impedance loops results in a timing difference between the currents in the secondary windings 11 and 12 and that a current pulse corresponding to this timing difference flows through the primary winding 10 causing the transformer core to be magnetically biased further.